1. Field of the Invention
The present invention relates to current-mode logic (CML) circuits, and more particularly to collector-dotted CML circuits.
2. Description of the Prior Art
Heretofore, a CML circuit has been known as one of the high speed logic circuits. The CML circuit has first and second transistors whose emitters are commonly connected, as its basic units. Of the two transistors the base of the first transistor serves as the input point of a logic signal, and the collector of the second transistor serves as the point of logic output. An emitter coupled logic (ECL) circuit which receives the logic output of a CML circuit with an emitter follower circuit is also frequently employed. These logic circuits are integrated on a silicon substrate as a large scale integrated circuit (LSI) to be used, for instance, as a gate array. Another example is an LSI employing field effect transistors that is integrated on a compound semiconductor substrate using such compound as gallium arsenide. Before proceeding further, it should be mentioned here that in the description that follows there sometimes occur cases in which an ECL circuit is also meant to represent a CML circuit.
In the fabrication of LSIs using CML circuits, when it is desired to construct a complicated logic circuit under the use of restricted supply voltages, there is sometimes employed a circuit known as a collector-dotted CML circuit. In this circuit, the collectors of the second transistors of a plurality of CML circuits are commonly connected.
An example of the use of the collector-dotted CML circuits is MC 10508, an OR-AND gated LSI, manufactured by Motorola, Inc. (see MECL Integrated Circuits Data Book, 1973). In the collector-dotted circuit used in this device, use is made of NPN transistors. Basically, in an individual CML circuit, the base of the first transistor is used as the input terminal of a logic signal while the base of the second transistor is used as the input terminal of a reference potential. The emitters of the first and the second transistors are connected commonly, and also connected to a constant current source or one end of a resistor which performs an operation equivalent to a constant current source. The other end of the constant current source or the resistor is connected to the low potential side of the power supply to the CML circuit. The collector of the second transistor is connected to one end of a load resistor, and the other end of the load resistor is connected to the high potential side of the power supply to the CML circuit. The collector of the second transistor becomes the logic output point of the CML circuit. A collector-dotted CML circuit is a circuit constructed by a plurality of individual CML circuits of the above description where the collectors of the first transistors of the respective CML circuits are connected commonly.
In the collector-dotted CML circuit as described in the above, when a logic signal at a low level (referred to as "L" hereinafter) is simultaneously input to the plurality of CML circuits, currents in number same as that of "L" inputs are supplied from the constant current sources. As a result, the potential at the point of logic output, namely, at the collector of the second transistor (although still at a low level) varies according to the input number of the "L" level signals. In order to reduce the variation, a diode is connected in parallel with the load resistor in the conventional device for clamping the voltage occurring across the load resistor. In the example mentioned above, however, a transistor is employed in place of such a diode.
However, when only one input assumes a logic signal "L" a current is supplied to the load from only one of the constant current sources. The voltage applied to the load is, since it is generally set to be lower than the clamping voltage, and the load resistance of the load is reduced due to the connection of the diode, is diminished than in the case where currents are supplied from a plurality of the constant current sources. Then, the potential at the logic output point is rasied, and as a result, the logic swing, which is defined as the amplitude between the low level and the high level (referred to as "H" hereinafter) where no current is supplied to the load resistor, is diminished.
The logic swing is normally set at 500 to 700 mV. In accordance with an experiment carried out using a collector-dotted CML circuit equivalent to the prior art device it was found that the logic swing was diminished from the value of 600 mV for the case where the load consisted exclusively of a resistor to 530 mV with a decrease of about 70 mV as a result of the connection of a diode. Accordingly, in order to obtain a noise margin equivalent to that in the case of a load consisting only of a resistor, it becomes necessary to increase the logic swing by about 10%. This implies the introduction of an adverse effect such as an increase in the power consumption or a deterioration in the switching speed.
Ordinarily, an electronic circuit such as a gate array that constitutes an LSI is a mixture of general CML circuits and collector-dotted CML circuits. In such a case, the activity ratio of the collector-dotted CML circuits is normally less than 10%. However, the high logic swing that is needed for the conventional collector-dotted CML circuits has to be applied also to all of the CML circuits which would not require it. As a result, the increase in the power consumption of the LSI or the deterioration in the switching speed amount as a whole to a large quantity.
Moreover, it was found that there was generated an increase in the collector-dotted CML circuit due to the presence of a parallel capacitance in the clamping diode that was provided in parallel to the load resistor.